GATE EC 2025 Set 1 Q35 — Sequential Circuits

A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input $P 0$ is set to logic '$0$ ' and $P 1$ is set to logic '$1$' at all times. The timing diagram of the inputs $S E L$ and $S$ are also shown below.

The sequence of output $Y$ from time $T_{0}$ to $T_{3}$ is _______.