GATE EC 2025 Set 1 Q52 — Sequential Circuits

In the circuit shown below, the $\mathrm{AND}$ gate has a propagation delay of $1 \: \mathrm{ ns}$. The edge-triggered flip-flops have a set-up time of $2 \: \mathrm{ ns}$, a hold-time of $0 \: \mathrm{ns}$, and a clock-to-$Q$ delay of $2$ ns.

The maximum clock frequency (in $\mathrm{MHz}$, rounded off to the nearest integer) such that there are no setup violations is $\_\_\_\_\_\_$