Official PYQ · 2017Set 1 · Q44Sequential CircuitsNAT2 marks

GATE EC 2017 Set 1 Q44 — Sequential Circuits

A $4$ -bit shift register circuit configured for right-shift operation, i.e. $D_{in}\rightarrow A,A\rightarrow B,B\rightarrow C,C\rightarrow D$ , is shown. If the present state of the shift register is $ABCD=1101$ , the number of clock cycles required to reach the state $ABCD=1111$ is _________.

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Answer: 10.0:10.0

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Published 10 Oct 2026

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