Official PYQ · 2017Set 1 · Q17Sequential CircuitsNAT1 mark

GATE EC 2017 Set 1 Q17 — Sequential Circuits

Consider the D-Latch shown in the figure, which is transparent when its clock input $CK$ is high and has zero propagation delay. In the figure , the clock signal $CLK$ has a $50 \%$ duty cycle and $CLK2$ is a one-fifth period delayed version of $CLK1$ .The duty cycle at the output of the latch in percentage is _________.

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Answer: 29.9:30.1

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Published 10 Oct 2026

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