GATE CS Sequential Circuits questions

Consider a $2$-bit saturating up/down counter that performs the saturating up count when the input $P$ is $0$, and the saturating down count when $P$ is $1$. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops. InputCureent StateNext State …

Consider the given sequential circuit designed using D-Flip-flops. The circuit is initialized with some value (initial state). The number of distinct states the circuit will go through before returning back to the initial state is ___________. (Answer in integer)

In a $4$-bit ripple counter, if the period of the waveform at the last flip-flop is $64$ microseconds, then the frequency of the ripple counter in kHz is _________. (Answer in integer)

Consider a sequential digital circuit consisting of $\mathrm{T}$ flip-flops and $\mathrm{D}$ flip-flops as shown in the figure. $\text{CLKIN}$ is the clock input to the circuit. At the beginning, $\text{Q1, Q2}$ and $\text{Q3}$ have values $0,1$ and $1,$ respectively. Which one of the given values of $\text{(Q1, Q2, Q3)}$ can $\text{NEVER}$ …

Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below: Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next three states?

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered $\text{D}$ flip-flops. The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ____

Consider a combination of $\text{T}$ and $\text{D}$ flip-flops connected as shown below. The output of the $\text{D}$ flip-flop is connected to the input of the $\text{T}$ flip-flop and the output of the $\text{T}$ flip-flop is connected to the input of the $\text{D}$ flip-flop. Initially, both $Q_{0}$ and $Q_{1}$ are set to $1$ (before the …

The next state table of a $2-$bit saturating up-counter is given below. $\begin{array}{cc|cc} Q_1 & Q_0 & Q_1^+ & Q_0^+ \\ \hline 0 & 0 & 0 & 1 \\ 0 & 1 & 1 & 0 \\ 1 & 0 & 1 & 1 \\ 1 & 1 & 1 & 1 \end{array}$ The counter is built as a synchronous sequential circuit using $T$ flip-flops. The …

We want to design a synchronous counter that counts the sequence $0-1-0-2-0-3$ and then repeats. The minimum number of $\text{J-K}$ flip-flops required to implement this counter is _____________.

A positive edge-triggered $D$ flip-flop is connected to a positive edge-triggered $JK$ flip-flop as follows. The $Q$ output of the $D$ flip-flop is connected to both the $J$ and $K$ inputs of the $JK$ flip-flop, while the $Q$ output of the $JK$ flip-flop is connected to the input of the $D$ flip-flop. Initially, the output of the $D$ …

Consider a $4$-bit Johnson counter with an initial value of $0000.$ The counting sequence of this counter is

The minimum number of $\text{JK}$ flip-flops required to construct a synchronous counter with the count sequence $(0, 0, 1, 1, 2, 2, 3, 3, 0, 0, \ldots)$ is _______.

Let $k=2^n$. A circuit is built by giving the output of an $n$-bit binary counter as input to an $n\text{-to-}2^n$ bit decoder. This circuit is equivalent to a

A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. If at some instance prior to the occurrence of the clock edge, $P, Q$ and $R$ have a value $0$, $1$ and $0$ respectively, what shall be the value of $PQR$ after the clock edge?

The minimum number of $\text{D}$ flip-flops needed to design a mod-258 counter is

Given the following state table of an FSM with two states $A$ and $B$,one input and one output. …

In an $SR$ latch made by cross-coupling two NAND gates, if both $S$ and $R$ inputs are set to $0$, then it will result in

A $\text{1-input}$, $\text{2-output}$ synchronous sequential circuit behaves as follows: Let $z_k, n_k$ denote the number of $0’s$ and $1’s$ respectively in initial $k$ bits of the input $(z_k+n_k=k)$. The circuit outputs $00$ until one of the following conditions holds. $z_k-n_k=2$. In this case, the output at the k-th and all subsequent …

Consider the circuit given below with initial state $Q_0=1, Q_1=Q_2=0$. The state of the circuit is given by the value $4Q_2+2Q_1+Q_0$ Which one of the following is correct state sequence of the circuit?