GATE CS 2004 Q18 — Sequential Circuits

An $SR$ latch constructed by cross-coupling two NAND gates has the following feedback equations for its outputs $Q$ and $Q'$:

When both inputs $S$ and $R$ are set to $0$ ($S = 0$ and $R = 0$):

• The output of the first NAND gate becomes: $$Q = \overline{0 \cdot Q'} = \overline{0} = 1$$
• The output of the second NAND gate becomes: $$Q' = \overline{0 \cdot Q} = \overline{0} = 1$$

Therefore, both outputs are forced to $1$, resulting in $Q = 1$ and $Q' = 1$.

Note: Although this is an invalid state for normal latch operation (since $Q$ and $Q'$ should be complements of each other), the physical outputs of the gates under these input conditions are indeed both $1$.