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Official PYQ · 2015

GATE CS 2015 Set 1 Q37 — Sequential Circuits

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A positive edge-triggered DD flip-flop is connected to a positive edge-triggered JKJK flip-flop as follows. The QQ output of the DD flip-flop is connected to both the JJ and KK inputs of the JKJK flip-flop, while the QQ output of the JKJK flip-flop is connected to the input of the DD flip-flop. Initially, the output of the DD flip-flop is set to logic one and the output of the JKJK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the QQ output of the JKJK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J=K=1J = K = 1 is the toggle mode and J=K=0J = K = 0 is the state holding mode of the JKJK flip-flops. Both the flip-flops have non-zero propagation delays.

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Answer: A

Let QD(n)Q_D(n) and QJK(n)Q_{JK}(n) represent the states of the DD and JKJK flip-flops at clock cycle nn, respectively. Based on the connections described:

  • The input to the DD flip-flop is D=QJK(n)D = Q_{JK}(n), so QD(n+1)=QJK(n)Q_D(n+1) = Q_{JK}(n).
  • The inputs to the JKJK flip-flop are J=K=QD(n)J = K = Q_D(n). This means:
    • If QD(n)=1Q_D(n) = 1, the JKJK flip-flop toggles: QJK(n+1)=QJK(n)‾Q_{JK}(n+1) = \overline{Q_{JK}(n)}.
    • If QD(n)=0Q_D(n) = 0, the JKJK flip-flop holds its state: QJK(n+1)=QJK(n)Q_{JK}(n+1) = Q_{JK}(n).

Given the initial state (n=0n=0) is QD(0)=1Q_D(0) = 1 and QJK(0)=0Q_{JK}(0) = 0, we can trace the states cycle-by-cycle:

Clock Cycle (nn) QD(n)Q_D(n) QJK(n)Q_{JK}(n) Next D=QJK(n)D = Q_{JK}(n) Next J=K=QD(n)J = K = Q_D(n)
00 (Initial) 11 00 00 11 (Toggle)
11 00 11 11 00 (Hold)
22 11 11 11 11 (Toggle)
33 11 00 00 11 (Toggle)
44 00 11 11 00 (Hold)

The sequence generated at the QQ output of the JKJK flip-flop (including the initial state) is 0,1,1,0,1,1,0,…0, 1, 1, 0, 1, 1, 0, \ldots, which corresponds to option A.

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