A positive edge-triggered flip-flop is connected to a positive edge-triggered flip-flop as follows. The output of the flip-flop is connected to both the and inputs of the flip-flop, while the output of the flip-flop is connected to the input of the flip-flop. Initially, the output of the flip-flop is set to logic one and the output of the flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the output of the flip-flop when the flip-flops are connected to a free-running common clock? Assume that is the toggle mode and is the state holding mode of the flip-flops. Both the flip-flops have non-zero propagation delays.
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Answer: A
Let and represent the states of the and flip-flops at clock cycle , respectively. Based on the connections described:
- The input to the flip-flop is , so .
- The inputs to the flip-flop are . This means:
- If , the flip-flop toggles: .
- If , the flip-flop holds its state: .
Given the initial state () is and , we can trace the states cycle-by-cycle:
| Clock Cycle () | Next | Next | ||
|---|---|---|---|---|
| (Initial) | (Toggle) | |||
| (Hold) | ||||
| (Toggle) | ||||
| (Toggle) | ||||
| (Hold) |
The sequence generated at the output of the flip-flop (including the initial state) is , which corresponds to option A.
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