GATE CS 2013 Q46 — Sequential Circuits

To construct a $16\text{K} \times 16$ RAM using $1\text{K} \times 8$ RAM chips, we first determine the arrangement of the memory chips:

1. Word size expansion (Columns): $$\frac{16\text{ bits}}{8\text{ bits}} = 2\text{ columns}$$ This means each row consists of 2 chips connected in parallel to achieve a 16-bit word length.
2. Capacity expansion (Rows): $$\frac{16\text{K}}{1\text{K}} = 16\text{ rows}$$ This means we need 16 distinct rows of chips, requiring a 1-of-16 row selection mechanism.

To select one of the 16 rows, we need a $4 \times 16$ decoder (since $\log_2(16) = 4$ address lines are required for row selection).

Now, we construct the $4 \times 16$ decoder using $2 \times 4$ decoders with enable lines:

• Output Stage: To get $16$ output lines, we need $\frac{16}{4} = 4$ decoders of size $2 \times 4$.
• Input/Control Stage: To enable exactly one of these $4$ decoders at a time, we need another $2 \times 4$ decoder whose outputs connect to the enable pins of the $4$ output-stage decoders.

$$\text{Total } 2 \times 4 \text{ decoders required} = 4 \text{ (output stage)} + 1 \text{ (control stage)} = 5$$

Thus, the number of $2 \times 4$ decoders needed is 5.