GATE CS Computer Organization and Architecture questions

Practise Computer Organization and Architecture questions for GATE CS. Explore official PYQs and original subject-wise quizzes, check answers and view available solutions. Free, no sign-in.

Track address sizes, cache organisation and pipeline dependencies carefully. Write down the units and assumptions before computing memory access times or processor performance.

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SubjectTopicYearType

Which of the following statements about synchronous and asynchronous I/O is NOT true?

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is:

Which of the following are NOT true in a pipelined processor? Bypassing can handle all RAW hazards Register renaming can eliminate all register carried WAR hazards Control hazard penalties can be eliminated by dynamic branch prediction

The use of multiple register windows with overlap causes a reduction in the number of memory accesses for: Function locals and parameters Register saves and restores Instruction fetches

For inclusion to hold between two cache levels

L_1

L_2

in a multi-level cache hierarchy, which of the following are necessary?

L_1

must be write-through cache

L_2

must be a write-through cache The associativity of

L_2

must be greater than that of

L_1

L_2

cache must be at least as large as the

L_1

Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor? It must be a trap instruction It must be a privileged instruction An exception cannot be allowed to occur during execution of an RFE instruction

Which of the following is/are true of the auto-increment addressing mode? It is useful in creating self-relocating code If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation The amount of increment depends on the size of the data item accessed

Consider the following program segment. Here

\text{R1, R2}

\text{R3}

are the general purpose registers. …

Consider the following program segment. Here

\text{R1, R2}

\text{R3}

are the general purpose registers. …

Consider a machine with a byte addressable main memory of

2^{16}

bytes. Assume that a direct mapped data cache consisting of

32

64

bytes each is used in the system. A

50

50

two-dimensional array of bytes is stored in the main memory starting from memory location

1100H

. Assume that the data cache is initially empty. The …

Consider a machine with a byte addressable main memory of

2^{16}

bytes. Assume that a direct mapped data cache consisting of

32

64

bytes each is used in the system. A

50 \times 50

two-dimensional array of bytes is stored in the main memory starting from memory location

1100H

. Assume that the data cache is initially empty. The …

Consider the following program segment. Here

\text{R1, R2}

\text{R3}

are the general purpose registers. …

In a simplified computer the instructions are: …

Consider a pipelined processor with the following four stages: IF: Instruction Fetch ID: Instruction Decode and Operand Fetch EX: Execute WB: Write Back The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need

1

clock cycle and …

4

-way set associative cache consisting of

128

lines with a line size of

64

words. The CPU generates a

20-bit

address of a word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively:

Consider two cache organizations. First one is

32

kB

2

-way set associative with

32

byte

block size, the second is of same size but direct mapped. The size of an address is

32

bits

in both cases . A

2

1

multiplexer has latency of

0.6 ns

k-

bit comparator has latency of

\frac{k}{10} ns

. The hit latency …

32

KB

direct mapped cache with

128

byte-block size. Suppose

A

is two dimensional array of size

512 \times512

with elements that occupy

8-bytes

each. Consider the following two

C

P1

P2

P1

: for (i=0; i<512; i++) { for (j=0; j<512; j++) { x +=A[i] [j]; } } P2: for (i=0; i<512; i++) …

32 KB

direct mapped cache with

128

byte-block size. Suppose A is two dimensional array of size

512 \times512

with elements that occupy

8

-bytes each. Consider the following two C code segments,

P1

P2

. P1: for (i=0; i<512; i++) { for (j=0; j<512; j++) { x +=A[i] [j]; } } P2: for (i=0; i<512; i++) { for (j=0; …

Consider two cache organizations. First one is

32 \; \textsf{KB}\;2\text{-way}

set associative with

32 \; \text{byte}

block size, the second is of same size but direct mapped. The size of an address is

32\; \text{bits}

in both cases . A

2\text{-to-}1

multiplexer has latency of

0.6 \; \text{ns}

k\text{-bit}

comparator has …

Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction “bbs reg, pos, label” jumps to label if bit in position pos of register operand reg is one. A register is

32

-bits wide and the bits are numbered

0

31,

bit in position

0

being the least significant. Consider the following emulation of this instruction on a …