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Official PYQ · 2007Q37Instruction PipeliningMCQ1 mark

GATE CS 2007 Q37 — Instruction Pipelining

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Consider a pipelined processor with the following four stages:

  • IF: Instruction Fetch
  • ID: Instruction Decode and Operand Fetch
  • EX: Execute
  • WB: Write Back

The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 11 clock cycle and the MUL instruction needs 33 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADDR2, R1, R0R2 ← R1+R0MULR4, R3, R2R4 ← R3∗R2SUBR6, R5, R4R6 ← R5−R4\begin{array}{ll} \textbf{ADD} & \text{R2, R1, R0} &&& \text{R2 $\leftarrow$ R1$+$R0} \\ \textbf{MUL} & \text{R4, R3, R2} &&& \text{R4 $\leftarrow$ R3$*$R2} \\ \textbf{SUB} & \text{R6, R5, R4} &&& \text{R6 $\leftarrow$ R5$-$R4} \\ \end{array}

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Answer: B

To find the total number of clock cycles, we trace the execution of the instructions through the pipeline stages (IF, ID, EX, WB) while accounting for data dependencies and operand forwarding.

  1. I1 (ADD R2, R1, R0):
    • IF: Cycle 1
    • ID: Cycle 2
    • EX: Cycle 3 (takes 1 cycle)
    • WB: Cycle 4
    • Note: The result R2R2 is ready at the end of Cycle 3.
  2. I2 (MUL R4, R3, R2):
    • IF: Cycle 2
    • ID: Cycle 3
    • EX: Cycles 4, 5, 6 (takes 3 cycles). Since R2R2 is forwarded from the end of Cycle 3, EX starts without any stall in Cycle 4.
    • WB: Cycle 7
    • Note: The result R4R4 is ready at the end of Cycle 6.
  3. I3 (SUB R6, R5, R4):
    • IF: Cycle 3
    • ID: Cycle 4
    • Stall: Cycles 5 and 6 (waiting for R4R4 to be computed by I2).
    • EX: Cycle 7 (takes 1 cycle). R4R4 is forwarded from the end of Cycle 6.
    • WB: Cycle 8

The pipeline execution schedule is summarized below:

Instruction C1 C2 C3 C4 C5 C6 C7 C8
I1 (ADD) IF ID EX WB - - - -
I2 (MUL) - IF ID EX1 EX2 EX3 WB -
I3 (SUB) - - IF ID stall stall EX WB

Thus, the sequence of instructions completes in 8 clock cycles.

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