A CPU has a direct mapped cache with byte-block size. Suppose A is two dimensional array of size with elements that occupy -bytes each. Consider the following two C code segments, and .
P1:
for (i=0; i<512; i++)
{
for (j=0; j<512; j++)
{
x +=A[i] [j];
}
}
P2:
for (i=0; i<512; i++)
{
for (j=0; j<512; j++)
{
x +=A[j] [i];
}
}
and are executed independently with the same initial state, namely, the array is not in the cache and , , are in registers. Let the number of cache misses experienced by be and that for be .
The value of is:
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Answer: C
To find the number of cache misses experienced by the program , we analyze the cache configuration and the array access pattern.
1. Cache and Array Parameters
- Cache block size:
- Array element size:
- Number of elements per cache block:
- Total elements in array :
2. Access Pattern in
In C, multi-dimensional arrays are stored in row-major order. The nested loops in access the elements as follows:
A[0][0], A[0][1], A[0][2], ..., A[0][511], A[1][0], ...
This represents a strictly sequential memory access pattern.
3. Cache Miss Calculation ()
- The first access results in a cache miss. This miss brings a block of consecutive elements ( to ) into the cache.
- The next accesses ( to ) are cache hits.
- The access results in another cache miss, loading the next elements.
Since the access is purely sequential and each element is accessed exactly once, there are no conflict misses affecting the active block. Thus, we experience exactly miss for every elements accessed.
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