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GATE CS 2006 Q80 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

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A CPU has a 32KB32 KB direct mapped cache with 128128 byte-block size. Suppose A is two dimensional array of size 512×512512 \times512 with elements that occupy 88-bytes each. Consider the following two C code segments, P1P1 and P2P2.

P1: 

for (i=0; i<512; i++)
{ 
    for (j=0; j<512; j++)
    { 
        x +=A[i] [j]; 
    } 
}

P2: 

for (i=0; i<512; i++)
{ 
    for (j=0; j<512; j++)
    { 
        x +=A[j] [i]; 
    } 
} 

P1P1 and P2P2 are executed independently with the same initial state, namely, the array AA is not in the cache and ii, jj, xx are in registers.  Let the number of cache misses experienced by P1P1 be M1M_{1}and that for P2P2 be M2M_{2}.

The value of M1M_{1} is:

Choose one option
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Answer: C

To find the number of cache misses M1M_1 experienced by the program P1P1, we analyze the cache configuration and the array access pattern.

1. Cache and Array Parameters

  • Cache block size: 128 bytes128\text{ bytes}
  • Array element size: 8 bytes8\text{ bytes}
  • Number of elements per cache block: 128 bytes8 bytes=16 elements\frac{128\text{ bytes}}{8\text{ bytes}} = 16\text{ elements}
  • Total elements in array AA: 512×512=262,144 elements512 \times 512 = 262,144\text{ elements}

2. Access Pattern in P1P1

In C, multi-dimensional arrays are stored in row-major order. The nested loops in P1P1 access the elements as follows:

A[0][0], A[0][1], A[0][2], ..., A[0][511], A[1][0], ...

This represents a strictly sequential memory access pattern.

3. Cache Miss Calculation (M1M_1)

  • The first access A[0][0]A[0][0] results in a cache miss. This miss brings a block of 1616 consecutive elements (A[0][0]A[0][0] to A[0][15]A[0][15]) into the cache.
  • The next 1515 accesses (A[0][1]A[0][1] to A[0][15]A[0][15]) are cache hits.
  • The 17th17^{\text{th}} access A[0][16]A[0][16] results in another cache miss, loading the next 1616 elements.

Since the access is purely sequential and each element is accessed exactly once, there are no conflict misses affecting the active block. Thus, we experience exactly 11 miss for every 1616 elements accessed.

Total Cache Misses M1=Total ElementsElements per Block=262,14416=16,384\text{Total Cache Misses } M_1 = \frac{\text{Total Elements}}{\text{Elements per Block}} = \frac{262,144}{16} = 16,384

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