GATE CS 2006 Q74 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

To find the hit latency $h_1$ of the 2-way set-associative cache, we first need to determine the size of the tag field ($k$ bits) in the address.

1. Address Division for 2-Way Set-Associative Cache

• Total Cache Size: $32 \text{ KB} = 2^{15} \text{ bytes}$
• Block Size: $32 \text{ bytes} = 2^5 \text{ bytes}$
• Number of Cache Blocks: $\frac{2^{15}}{2^5} = 2^{10} = 1024$ blocks
• Set Size: $2$ blocks (since it is $2$-way set-associative)
• Number of Sets: $\frac{1024}{2} = 512 = 2^9$ sets

The $32$-bit physical address is divided as follows:

2. Calculating Hit Latency ($h_1$)

In a 2-way set-associative cache, the hit path consists of two main sequential steps after the set is indexed:

1. Tag Comparison: Comparing the $18$-bit tag of the incoming address with the tags of the two blocks in the selected set using $18$-bit comparators in parallel. $$\text{Comparator Latency} = \frac{k}{10} = \frac{18}{10} = 1.8 \text{ ns}$$
2. Data Selection (Multiplexing): A $2\text{-to-}1$ multiplexer selects the data from the correct block based on the comparator output. $$\text{Multiplexer Latency} = 0.6 \text{ ns}$$

Therefore, the total hit latency $h_1$ is:

Thus, the correct option is A.