GATE CS 2007 Q10 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

To determine the size of the TAG, LINE (Set Index), and WORD (Offset) fields, we analyze the structure of the $20$-bit physical address generated by the CPU:

$$\text{Address Format: } [\text{ TAG } (t \text{ bits}) \mid \text{ LINE } (s \text{ bits}) \mid \text{ WORD } (w \text{ bits})]$$

1. WORD Field ($w$):
   The block size (line size) is given as $64$ words. $$\text{WORD bits } (w) = \log_2(64) = 6 \text{ bits}$$
2. LINE Field ($s$):
   The cache is $4$-way set associative and contains a total of $128$ lines. $$\text{Number of Sets} = \frac{\text{Total Lines}}{\text{Associativity}} = \frac{128}{4} = 32 \text{ sets}$$ $$\text{LINE bits } (s) = \log_2(32) = 5 \text{ bits}$$
3. TAG Field ($t$):
   The total address size is $20$ bits. $$\text{TAG bits } (t) = \text{Total Address Bits} - (s + w)$$ $$t = 20 - (5 + 6) = 9 \text{ bits}$$

Thus, the number of bits in the TAG, LINE, and WORD fields are respectively $9, 5, 6$.