GATE CS 2008 Q38 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

To determine the earliest stage at which the data Translation Lookaside Buffer (dTLB) can be accessed, let us understand its role and requirements:

1. Role of the dTLB: The dTLB is a high-speed cache used to translate the virtual address of data into its corresponding physical address.
2. Input to the dTLB: To perform a translation lookup, the dTLB requires the virtual address (specifically, the virtual page number) of the memory operand.
3. Effective Address (EA) Calculation: In a pipeline, the virtual address of a data operand is known as the Effective Address. It is computed during the execution stage (or address generation stage) by adding components like base registers, index registers, and displacements (e.g., $\text{EA} = \text{Base} + \text{Displacement}$).

Since the virtual address is not known until this calculation is finished, the dTLB lookup cannot begin beforehand. Therefore, the earliest the dTLB can be accessed is after effective address calculation has completed.

Why other options are incorrect:

• Options A & B: The complete virtual address is not yet available, so a lookup is impossible.
• Option D: In many modern processors, the TLB lookup and the cache lookup (specifically for Virtually Indexed Physically Tagged caches) are initiated in parallel, or the TLB lookup is done before the physical cache tag comparison. Waiting until the data cache lookup completes is unnecessarily late.