GATE CS 2008 Q36 — Instruction Pipelining

To determine which of the statements are NOT true, let us analyze each statement individually:

• Statement I: Bypassing can handle all RAW hazards (NOT TRUE)
  Bypassing (or operand forwarding) can resolve many Read-After-Write (RAW) hazards by routing the execution result directly to the dependent instruction. However, it cannot resolve all RAW hazards. For example, in a load-use hazard (where a load instruction is immediately followed by an instruction that uses the loaded register), the data is not available until the end of the Memory (MEM) stage. Thus, a pipeline stall (bubble) is mandatory in addition to bypassing.


• Statement II: Register renaming can eliminate all register carried WAR hazards (TRUE)
  Write-After-Read (WAR) and Write-After-Write (WAW) hazards are name dependencies (false dependencies) caused by a limited number of architectural registers. By using register renaming, the processor maps architectural registers to a larger set of physical registers, thereby completely eliminating WAR and WAW hazards.


• Statement III: Control hazard penalties can be eliminated by dynamic branch prediction (NOT TRUE)
  Dynamic branch prediction significantly reduces control hazard penalties by predicting the branch outcome at runtime. However, it cannot eliminate them entirely because branch predictors are not $100\%$ accurate. Whenever a misprediction occurs, the pipeline must be flushed, which incurs a penalty.

Since Statements I and III are NOT true, the correct option is B.