GATE EC Digital Circuits questions

In the circuit shown in the Figure, $A$ and $B$ are logic inputs and $Y$ is the logic output. Which of the following logic operations is realized by the circuit?

A binary ripple counter is designed to count $(0)_{10}$ to $(64)_{10}$. Which of the following is/are the number of flip-flops required to design the counter?

The negative edge triggered JK flip-flop in the Figure has J and K inputs tied to Logic High and a square wave of $10$ cycles/second is applied to its clock (C) input. The frequency of the output Q (in cycles/second) is $\_\_\_\_$. (rounded off to two decimal places)

The address of the first location of a $256$ kilo byte $(\mathrm{KB})$ memory is $(2500)_{\mathrm{H}}$. Choose the correct address of the last location of the memory.

What is the $10^{\prime} s$ complement of $(47)_{10}?$

A Boolean function, $f(x, y, z)$ with $x$ as MSB and $z$ as LSB is realized by $4: 1$ multiplexer (MUX) with select lines, $\mathrm{S}_{1}$ and $\mathrm{S}_{0}\left(\mathrm{~S}_{1}\right.$ is MSB, $\mathrm{S}_{0}$ is LSB) and inputs, $\mathrm{I}_{0}, \mathrm{I}_{1}, \mathrm{I}_{2}, \mathrm{I}_{3}$ as shown in the Figure. Which of the …

A shift-left Shift Register (SR) and a D flip-flop are connected to a synchronized clock as shown in the Figure. Assume that the SR and D flip-flops are initially cleared and the XOR gate has no propagation delay. Which of the following options gives the correct binary representation $\left(b_{7} b_{6} b_{5} b_{4} b_{3} b_{2} b_{1} b_{0}\right)$ of the …

Consider the four-variable Boolean function, $f(w, x, y, z)=\sum m(0,2,5,7,8,10,13,14,15)$ with '$w$' as MSB and '$z$' as LSB. Which of the following expressions is/are the valid form(s) of $f(w, x, y, z)?$

A $3$-input majority logic gate has inputs $X, Y$, and $Z$. The output $F$ of the gate is logic '$1$' if two or more of the inputs are logic '$1$'. The output $F$ is logic '$0$' if two or more of the inputs are logic '$0$'. Which one of the following options is a Boolean expression of the output $F$ ?

A full adder and an XOR gate are used to design a digital circuit with inputs $X, Y$, and $Z$, and output $F$, as shown below. The input $Z$ is connected to the carry-in input of the full adder. If the input $Z$ is set to logic ' $l$ ', then the circuit functions as $\_\_\_\_\_\_\_$ with $X$ and $Y$ as inputs.

A $4$-bit weighted-resistor DAC with inputs $b_{3}, b_{2}, b_{1}$, and $b_{0}$ (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when the corresponding input bits are logic ' $l$ ' and open otherwise. When the input $b_{3} b_{2} b_{1} b_{0}$ changes from $1110$ to $1101$, the magnitude of the change in the …

A $10$-bit analog-to-digital converter (ADC) has a sampling frequency of $1\: \mathrm{MHz}$ and a full scale voltage of $3.3 \: \mathrm{V}$. For an input sinusoidal signal with frequency $500 \: \mathrm{kHz}$ , the maximum SNR (in $\mathrm{dB}$ , rounded off to two decimal places) and the data rate (in $\mathrm{Mbps}$) at the output of the ADC …

A positive-edge-triggered sequential circuit is shown below. There are no timing violations in the circuit. Input $P 0$ is set to logic '$0$ ' and $P 1$ is set to logic '$1$' at all times. The timing diagram of the inputs $S E L$ and $S$ are also shown below. The sequence of output $Y$ from time $T_{0}$ to $T_{3}$ is _______.

In the circuit shown below, the $\mathrm{AND}$ gate has a propagation delay of $1 \: \mathrm{ ns}$. The edge-triggered flip-flops have a set-up time of $2 \: \mathrm{ ns}$, a hold-time of $0 \: \mathrm{ns}$, and a clock-to-$Q$ delay of $2$ ns. The maximum clock frequency (in $\mathrm{MHz}$, rounded off to the nearest integer) such that there …

​​​​For the Boolean function $$F(A, B, C, D)=\sum m(0,2,5,7,8,10,12,13,14,15) \text{, }$$ the essential prime implicants are $\_\_\_\_\_\_$.

A machine has a $32$-bit architecture with $1$-word long instructions. It has $24$ registers and supports an instruction set of size $40$. Each instruction has five distinct fields, namely opcode, two source register identifiers, one destination register identifier, and an immediate value. Assuming that the immediate operand is an unsigned integer, …

In a number system of base $r$, the equation $x^{2}-12 x+37=0$ has $x=8$ as one of its solutions. The value of $r$ is $\_\_\_\_\_\_\_$.

As shown in the circuit, the initial voltage across the capacitor is $10 \mathrm{~V}$, with the switch being open. The switch is then closed at $t=0$. The total energy dissipated in the ideal Zener diode $\left(V_{Z}=5 \mathrm{~V}\right)$ after the switch is closed (in $\mathrm{mJ}$, rounded off to three decimal places) is $\_\_\_\_\_\_$.

​​​​​A $4$-bit priority encoder has inputs $D_{3}, D_{2}, D_{1}$, and $D_{0}$ in descending order of priority. The two-bit output $A B$ is generated as $00,01,10$, and 11 corresponding to inputs $D_{3}, D_{2}, D_{1}$, and $D_{0}$, respectively. The Boolean expression of the output bit $B$ is $\_\_\_\_\_\_\_$.

​​​​​The propagation delay of the $2 \times 1$ MUX shown in the circuit is $10 \mathrm{~ns}$. Consider the propagation delay of the inverter as $0 \mathrm{~ns}$. If $\text{S}$ is set to $1$ then the output $\text{Y}$ is $\_\_\_\_\_\_$.