Official PYQ · 2025Set 1 · Q25Data ConvertersNAT1 mark

GATE EC 2025 Set 1 Q25 — Data Converters

A $4$ -bit weighted-resistor DAC with inputs $b_{3}, b_{2}, b_{1}$ , and $b_{0}$ (MSB to LSB) is designed using an ideal opamp, as shown below. The switches are closed when the corresponding input bits are logic ' $l$ ' and open otherwise.

When the input $b_{3} b_{2} b_{1} b_{0}$ changes from $1110$ to $1101$ , the magnitude of the change in the output voltage $V_{O}$ (in mV , rounded off to the nearest integer) is $\_\_\_\_\_\_$

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Answer: 250:250

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Published 10 Oct 2026

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