GATE CS Computer Organization and Architecture questions

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Track address sizes, cache organisation and pipeline dependencies carefully. Write down the units and assumptions before computing memory access times or processor performance.

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SubjectTopicYearType

The instruction pipeline of a RISC processor has the following stages: Instruction Fetch

(IF)

, Instruction Decode

(ID)

, Operand Fetch

(OF)

, Perform Operation

(PO)

(WB)

IF

ID

OF

WB

1

clock cycle each for every instruction. Consider a sequence of

100

instructions. In the

PO

The size of the physical address space of a processor is

2^P

bytes. The word length is

2^W

bytes. The capacity of cache memory is

2^N

bytes. The size of each cache block is

2^M

K

-way set-associative cache memory, the length (in number of bits) of the tag field is

32\text{-bit}

wide main memory unit with a capacity of

1\;\textsf{GB}

256\textsf{M} \times 4\text{-bit}

DRAM chips. The number of rows of memory cells in the DRAM chip is

2^{14}

. The time taken to perform one refresh operation is

50\;\text{nanoseconds}

. The refresh period is

2\;\text{milliseconds.}

The percentage …

Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor?

A cache memory unit with capacity of

N

words and block size of

B

words is to be designed. If it is designed as a direct mapped cache, the length of the

\textsf{TAG}

10

bits. If the cache unit is now designed as a

16

-way set-associative cache, the length of the

\textsf{TAG}

field is ____________ bits.

2

-way set associative cache with

256

blocks and uses

\text{LRU}

replacement. Initially the cache is empty. Conflict misses are those misses which occur due to the contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of access to memory blocks : …

Instruction execution in a processor is divided into

5

stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 …

Consider a RISC machine where each instruction is exactly

4

bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the …

Consider a two-level cache hierarchy with

L1

L2

caches. An application incurs

1.4

memory accesses per instruction on average. For this application, the miss rate of

L1

0.1

L2

cache experiences, on average,

7

1000

instructions. The miss rate of

L2

expressed correct to two decimal places is …

C

struct defined below: struct data { int marks [100]; char grade; int cnumber; }; struct data student; The base address of student is available in register

R1

. The field student.grade can be accessed efficiently using:

Consider a machine with a byte addressable main memory of

2^{32}

bytes divided into blocks of size

32

bytes. Assume that a direct mapped cache having

512

cache lines is used with this machine. The size of the tag field in bits is _______

The read access times and the hit ratios for different caches in a memory hierarchy are as given below: …

In a two-level cache system, the access times of

L_1

L_2

1

8

clock cycles, respectively. The miss penalty from the

L_2

cache to main memory is

18

clock cycles. The miss rate of

L_1

cache is twice that of

L_2

. The average memory access time (AMAT) of this cache system is

2

cycles. The miss rates of …

The size of the data count register of a

\text{DMA}

16\;\text{bits}

. The processor needs to transfer a file of

29,154

kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the

\text{DMA}

controller needs to get the control of the system bus from the processor to transfer the file from …

The stage delays in a

4

-stage pipeline are

800, 500, 400

300

picoseconds. The first stage (with delay

800

picoseconds) is replaced with a functionality equivalent design involving two stages with respective delays

600

350

picoseconds. The throughput increase of the pipeline is ___________ percent.

A processor can support a maximum memory of

4\;\textsf{GB}

, where the memory is word-addressable (a word consists of two bytes). The size of address bus of the processor is at least _________bits.

Suppose the functions

F

G

can be computed in

5

3

nanoseconds by functional units

U_{F}

U_{G}

, respectively. Given two instances of

U_{F}

and two instances of

U_{G}

, it is required to implement the computation

F(G(X_{i}))

1 \leq i \leq 10

. Ignoring all other delays, the minimum time required to complete …

The width of the physical address on a machine is

40

bits. The width of the tag field in a

512

8

-way set associative cache is ________ bits.

Consider a processor with

64

registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has

100

instructions, the …

A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is

1

ms and to read a block from the disk is

10

ms. Assume that the cost of checking whether a block exists in the cache is negligible. Available cache sizes are in multiples of

10