Instruction execution in a processor is divided into stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2 ns. Two pipelined implementation of the processor are contemplated:
- a naive pipeline implementation (NP) with stages and
- an efficient pipeline (EP) where the OF stage is divided into stages and with execution times of 12 ns and 8 ns respectively.
The speedup (correct to two decimal places) achieved by EP over NP in executing independent instructions with no hazards is _________ .
View worked solution
Answer: 1.50 : 1.51
The execution time of a pipeline with stages for instructions (with no hazards) is given by:
where is the clock cycle time, determined by the maximum stage delay plus the buffer overhead:
1. Naive Pipeline (NP)
- Stages (): (IF, ID, OF, EX, WB)
- Stage delays: ns
- Buffer delay: ns
- Clock cycle time ():
- Total execution time for instructions ():
2. Efficient Pipeline (EP)
- Stages (): (IF, ID, OF1, OF2, EX, WB)
- Stage delays: ns
- Buffer delay: ns
- Clock cycle time ():
- Total execution time for instructions ():
3. Speedup Calculation
The speedup achieved by EP over NP is:
Rounding to two decimal places, the speedup is 1.51 (or 1.50 depending on the rounding convention used, both are accepted).
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