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Official PYQ · 2017

GATE CS 2017 Set 1 Q25 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

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Consider a two-level cache hierarchy with L1L1 and L2L2 caches. An application incurs 1.41.4 memory accesses per instruction on average. For this application, the miss rate of L1L1 cache is 0.10.1; the L2L2 cache experiences, on average, 77 misses per 10001000 instructions. The miss rate of L2L2 expressed correct to two decimal places is ________.
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Answer: 0.05

To find the local miss rate of the L2L2 cache, we need to determine the ratio of L2L2 misses to L2L2 accesses.

1. Calculate L2L2 Accesses per Instruction

Every memory access first goes to the L1L1 cache. If it misses in L1L1, it is then directed to the L2L2 cache. Therefore, the number of accesses to the L2L2 cache is equal to the number of misses in the L1L1 cache.

  • Memory accesses per instruction: 1.41.4
  • L1L1 miss rate (MRL1MR_{L1}): 0.10.1

Accesses to L2 per instruction=Misses in L1 per instruction\text{Accesses to } L2 \text{ per instruction} = \text{Misses in } L1 \text{ per instruction} Accesses to L2=1.4×0.1=0.14 accesses/instruction\text{Accesses to } L2 = 1.4 \times 0.1 = 0.14 \text{ accesses/instruction}

2. Calculate L2L2 Misses per Instruction

We are given that the L2L2 cache experiences 77 misses per 10001000 instructions.

Misses in L2 per instruction=71000=0.007 misses/instruction\text{Misses in } L2 \text{ per instruction} = \frac{7}{1000} = 0.007 \text{ misses/instruction}

3. Calculate L2L2 Miss Rate

The local miss rate of the L2L2 cache (MRL2MR_{L2}) is the fraction of L2L2 accesses that result in a miss:

MRL2=Misses in L2 per instructionAccesses to L2 per instructionMR_{L2} = \frac{\text{Misses in } L2 \text{ per instruction}}{\text{Accesses to } L2 \text{ per instruction}} MRL2=0.0070.14=7140=0.05MR_{L2} = \frac{0.007}{0.14} = \frac{7}{140} = 0.05

Thus, the miss rate of the L2L2 cache is 0.05.

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