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GATE CS 2018 Q34 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

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The size of the physical address space of a processor is 2P2^P bytes. The word length is 2W2^W bytes. The capacity of cache memory is 2N2^N bytes. The size of each cache block is 2M2^M words. For a KK-way set-associative cache memory, the length (in number of bits) of the tag field is

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Answer: B

To find the length of the tag field in a KK-way set-associative cache, we can divide the physical address into three fields: Tag, Set Index, and Block Offset.

1. Physical Address Length:
The size of the physical address space is 2P2^P bytes. Thus, the total physical address length is PP bits.

2. Block Offset Bits:

  • Word length = 2W2^W bytes
  • Block size = 2M2^M words = 2M×2W2^M \times 2^W bytes = 2M+W2^{M+W} bytes
Therefore, the block offset requires M+WM + W bits.

3. Set Index Bits:

  • Total cache capacity = 2N2^N bytes
  • Number of blocks in the cache = Cache CapacityBlock Size=2N2M+W=2N−M−W\frac{\text{Cache Capacity}}{\text{Block Size}} = \frac{2^N}{2^{M+W}} = 2^{N - M - W}
  • For a KK-way set-associative cache, the number of sets is:
    Number of Sets=Total BlocksK=2N−M−WK=2N−M−W−log⁡2K\text{Number of Sets} = \frac{\text{Total Blocks}}{K} = \frac{2^{N-M-W}}{K} = 2^{N - M - W - \log_2 K}
Therefore, the set index requires N−M−W−log⁡2KN - M - W - \log_2 K bits.

4. Tag Bits:
The sum of the fields must equal the total physical address length PP: Tag bits+Set index bits+Block offset bits=P\text{Tag bits} + \text{Set index bits} + \text{Block offset bits} = P Tag bits+(N−M−W−log⁡2K)+(M+W)=P\text{Tag bits} + (N - M - W - \log_2 K) + (M + W) = P Tag bits+N−log⁡2K=P\text{Tag bits} + N - \log_2 K = P Tag bits=P−N+log⁡2K\text{Tag bits} = P - N + \log_2 K

Thus, the correct option is B.

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