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Official PYQ · 2018

GATE CS 2018 Q50 — Instruction Pipelining

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The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF)(IF), Instruction Decode (ID)(ID), Operand Fetch (OF)(OF), Perform Operation (PO)(PO) and Writeback (WB)(WB), The IFIF, IDID, OFOF and WBWB stages take 11 clock cycle each for every instruction. Consider a sequence of 100100 instructions. In the POPO stage, 4040 instructions take 33 clock cycles each, 3535 instructions take 22 clock cycles each, and the remaining 2525 instructions take 11 clock cycle each. Assume that there are no data hazards and no control hazards.

The number of clock cycles required for completion of execution of the sequence of instruction is _____.
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Answer: 219

Since there are no data or control hazards, instructions flow through the pipeline sequentially. The stages before and after the Perform Operation (POPO) stage are IFIF, IDID, OFOF (each taking 11 cycle) and WBWB (taking 11 cycle).

Because the POPO stage takes at least 11 clock cycle for every instruction, it acts as the bottleneck. Once the first instruction reaches the POPO stage, the POPO stage will run continuously without any idle cycles until all 100100 instructions complete their POPO stage.

We can calculate the total clock cycles as follows:

  • Cycles before POPO for the first instruction: 33 cycles (IFIF, IDID, and OFOF)
  • Total cycles spent in the POPO stage for all 100100 instructions:
    Total PO cycles=(40×3)+(35×2)+(25×1)=120+70+25=215 cycles\text{Total } PO \text{ cycles} = (40 \times 3) + (35 \times 2) + (25 \times 1) = 120 + 70 + 25 = 215 \text{ cycles}
  • Cycles after POPO for the last instruction: 11 cycle (WBWB)

Total Clock Cycles=3+215+1=219 cycles\text{Total Clock Cycles} = 3 + 215 + 1 = 219 \text{ cycles}

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