Skip to content
Official PYQ · 2016

GATE CS 2016 Set 2 Q32 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

Explain with AI
The width of the physical address on a machine is 4040 bits. The width of the tag field in a 512512 KB 88-way set associative cache is ________ bits.
View worked solution

Answer: 24

In a set-associative cache, the physical address is divided into three fields:

Physical Address=Tag+Set Index+Block Offset\text{Physical Address} = \text{Tag} + \text{Set Index} + \text{Block Offset}

Let:

  • ss be the number of bits for the Set Index.
  • bb be the number of bits for the Block Offset.

The total number of bytes in one way of the cache (or the size of each set's capacity contribution) is given by:

Number of Sets×Block Size=Cache SizeAssociativity\text{Number of Sets} \times \text{Block Size} = \frac{\text{Cache Size}}{\text{Associativity}}

Taking the base-2 logarithm on both sides gives the combined bits for the Set Index and Block Offset:

s+b=log⁡2(Cache SizeAssociativity)s + b = \log_2\left(\frac{\text{Cache Size}}{\text{Associativity}}\right)

Given:

  • Cache Size=512 KB=219 bytes\text{Cache Size} = 512\text{ KB} = 2^{19}\text{ bytes}
  • Associativity=8=23\text{Associativity} = 8 = 2^3

Substituting these values:

s+b=log⁡2(21923)=log⁡2(216)=16 bitss + b = \log_2\left(\frac{2^{19}}{2^3}\right) = \log_2(2^{16}) = 16\text{ bits}

Since the total physical address width is 4040 bits, the width of the tag field is:

Tag bits=Physical Address Width−(s+b)\text{Tag bits} = \text{Physical Address Width} - (s + b)

Tag bits=40−16=24 bits\text{Tag bits} = 40 - 16 = 24\text{ bits}

Free practice · Your answers on this page are not saved.

Published
Report a correction
Keep exploringMore Memory Hierarchy: Cache, Main Memory and Secondary Storage questions