GATE CS Computer Organization and Architecture questions
Practise Computer Organization and Architecture questions for GATE CS. Explore official PYQs and original subject-wise quizzes, check answers and view available solutions. Free, no sign-in.
Track address sizes, cache organisation and pipeline dependencies carefully. Write down the units and assumptions before computing memory access times or processor performance.
Subject, topic, year and type filter the full library. Match any choice within a filter, and all selected filter categories. Search, source and sort apply to this page.
20 on this page
A CPU has a five-stage pipeline and runs at GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions following a conditional branch until the branch outcome is …
A CPU has a cache with block size bytes. The main memory has banks, each bank being bytes wide. Consecutive − byte chunks are mapped on consecutive banks with wrap-around. All the banks can be accessed in parallel, but two accesses to the same bank must be serialized. A cache block access may involve multiple iterations of …
A CPU has - instructions. A program starts at address (in decimal). Which one of the following is a legal program counter (all values in decimal)?
Consider the following data path of a The the bus and all the registers in the data path are of identical size. All operations including incrementation of the and the are to be carried out in the Two clock cycles are needed for memory read operation – the first one for loading …
Consider the following data path of a The the bus and all the registers in the data path are of identical size. All operations including incrementation of the and the are to be carried out in the Two clock cycles are needed for memory read operation – the first one for loading …
A device with data transfer rate KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be sec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under …
Consider a disk drive with the following specifications: surfaces, tracks/surface, sectors/track, KB/sector, rotation speed rpm. The disk is operated in cycle stealing mode whereby whenever one byte word is ready it is sent to memory; similarly, for writing, the disk interface reads a byte word from the …
A stage pipelined CPU has the following sequence of stages: IF – instruction fetch from instruction memory RD – Instruction decode and register read EX – Execute: ALU operation for data and address computation MA – Data memory access – for write access, the register read at RD state is used. WB – Register write back Consider the following sequence of …
Consider a direct mapped cache of size with block size . The generates addresses. The number of bits needed for cache indexing and the number of tag bits are respectively,
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side. …
Consider a three word machine instruction The first operand (destination) uses indexed addressing mode with as the index register. The second operand (source) uses indirect addressing mode. and are memory addresses residing at the second and third words, respectively. The first word of the …
Consider the following program segment for a hypothetical CPU having three user registers and \begin{array}{|l|l|c|} \hline \text {Instruction} & \text{Operation }& \text{Instruction size (in Words)} \\\hline \text{MOV } & \text{} \leftarrow \text{Memory}& \text{} \\\hline\text{MOV …
A 4-stage pipeline has the stage delays as , , and , respectively. Registers that are used between the stages have a delay of each. Assuming constant clocking rate, the total time taken to process data items on this pipeline will be:
A hard disk with a transfer rate of Mbytes/second is constantly transferring data to memory using DMA. The processor runs at MHz, and takes and clock cycles to initiate and complete DMA transfer respectively. If the size of the transfer is Kbytes, what is the percentage of processor time consumed for the transfer …
The microinstructions stored in the control memory of a processor have a width of bits. Each microinstruction is divided into three fields: a micro-operation field of bits, a next address field and a MUX select field There are status bits in the input of the MUX. How many bits are there in the and fields, and …
Consider a small two-way set-associative cache memory, consisting of four blocks. For choosing the block to be replaced, use the least recently used (LRU) scheme. The number of cache misses for the following sequence of block addresses is: .
Consider the following program segment for a hypothetical CPU having three user registers and …
Which of the following addressing modes are suitable for program relocation at run time? Absolute addressing Based addressing Relative addressing Indirect addressing
Consider a system with a two-level paging scheme in which a regular memory access takes , and servicing a page fault takes . An average instruction takes nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is %, and the page fault rate is one in every instructions. What is …
Consider the following assembly language program for a hypothetical processor and are bit registers. The meanings of various instructions are shown as comments. MOV B, #0 ; MOV C, #8 ; Z: CMP C, #0 ; compare C with 0 JZ X ; jump to X if zero flag is set SUB C, #1 ; RRC A, #1 ; right …