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Official PYQ · 2004Q64Machine Instructions and Addressing ModesMCQ1 mark

GATE CS 2004 Q64 — Machine Instructions and Addressing Modes

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Consider the following program segment for a hypothetical CPU having three user registers R1,R2R_1, R_2 and R3.R_3.

\begin{array}{|l|l|c|} \hline \text {Instruction}  &  \text{Operation }& \text{Instruction size (in Words)} \\\hline \text{MOV R1,5000R_1,5000} 
& \text{R1R1} \leftarrow  \text{Memory[5000][5000]}& \text{22} \\\hline\text{MOV R2(R1)R_2(R_1)} & \text{R2R2} \leftarrow  \text{Memory[(R1)][(R_1)]}& \text{11} \\\hline \text{ADD R2,R3R_2,R_3} & \text{R2R_2} \leftarrow  \text{R2+R3R_2 + R_3} & \text{11} \\\hline \text{MOV 6000,R26000,R_2} & \text{Memory[6000][6000]} \leftarrow  \text{R2R_2} & \text{22} \\\hline \text{Halt} & \text{Machine Halts} & \text{11} \\\hline \end{array}

Let the clock cycles required for various operations be as follows:

\begin{array}{|l|l|} \hline \text {Register to/from memory transfer}  &  \text{3 clock cycles } \\\hline  \text {ADD with both operands in register}  &  \text{1 clock cycles } \\\hline \text {Instruction fetch and decode}  &  \text{2 clock cycles }\\\hline \end{array}

The total number of clock cycles required to execute the program is

Choose one option
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Answer: B

To find the total number of clock cycles required to execute the program, we need to calculate the cycles spent on Instruction Fetch & Decode and Execution for each instruction.

1. Instruction Fetch and Decode Cycles

Since the instruction sizes are specified in words, the fetch and decode operation must be performed for each word of the instruction. Thus, the fetch and decode cost is:

Fetch & Decode Cycles=Instruction Size (in words)×2 clock cycles\text{Fetch \& Decode Cycles} = \text{Instruction Size (in words)} \times 2 \text{ clock cycles}

2. Execution Cycles

  • Register to/from memory transfer: 33 clock cycles
  • ADD with both operands in registers: 11 clock cycle
  • Halt: 00 additional execution cycles (only fetch and decode is needed to halt the machine)

Step-by-Step Calculation

Instruction Size (Words) Fetch & Decode Cycles Execution Cycles Total Cycles
MOV R1, 5000 2 2×2=42 \times 2 = 4 33 (Memory →\rightarrow Register) 4+3=74 + 3 = 7
MOV R2, (R1) 1 1×2=21 \times 2 = 2 33 (Memory →\rightarrow Register) 2+3=52 + 3 = 5
ADD R2, R3 1 1×2=21 \times 2 = 2 11 (Register-to-Register ADD) 2+1=32 + 1 = 3
MOV 6000, R2 2 2×2=42 \times 2 = 4 33 (Register →\rightarrow Memory) 4+3=74 + 3 = 7
Halt 1 1×2=21 \times 2 = 2 00 2+0=22 + 0 = 2

Summing the total cycles for all instructions:

Total Clock Cycles=7+5+3+7+2=24 cycles\text{Total Clock Cycles} = 7 + 5 + 3 + 7 + 2 = 24 \text{ cycles}

Therefore, the correct option is B.

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