Official PYQ · 2005Q68Instruction PipeliningMCQ1 mark

GATE CS 2005 Q68 — Instruction Pipelining

A $5$ stage pipelined CPU has the following sequence of stages:

IF – instruction fetch from instruction memory
RD – Instruction decode and register read
EX – Execute: ALU operation for data and address computation
MA – Data memory access – for write access, the register read at RD state is used.
WB – Register write back

Consider the following sequence of instructions:

Let each stage take one clock cycle.

What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of $I_1$ ?

View worked solution

Answer: A

To find the number of clock cycles, we analyze the dependencies between instructions assuming standard operand forwarding is supported:

$I_1 \rightarrow I_2$ (Load-Use Hazard): $I_1$ is a load instruction ( $R0 \Leftarrow M[loc1]$ ). The data for $R0$ is only available at the end of the MA stage of $I_1$ . Since $I_2$ needs $R0$ at the beginning of its EX stage, $I_2$ must stall for $1$ clock cycle in its RD stage. The operand is then forwarded from the MA/WB register of $I_1$ to the EX stage of $I_2$ .
$I_2 \rightarrow I_3$ (ALU-ALU Dependency): $I_2$ is an arithmetic instruction ( $R0 \Leftarrow R0 + R0$ ). The result is available at the end of the EX stage of $I_2$ . Since $I_3$ needs $R0$ for its EX stage, the value can be forwarded directly from the EX/MA register of $I_2$ to the EX stage of $I_3$ without any stalls.

The cycle-by-cycle pipeline execution is shown below:

Clock Cycle	$I_1$	$I_2$	$I_3$
1	IF
2	RD	IF
3	EX	RD	IF
4	MA	RD (stall)	IF (stall)
5	WB	EX	RD
6		MA	EX
7		WB	MA
8			WB

Thus, the sequence of instructions completes in 8 clock cycles.

Free practice · Your answers on this page are not saved.

Published 10 Oct 2026

Related questions