Consider the following data path of a
The the bus and all the registers in the data path are of identical size. All operations including incrementation of the and the are to be carried out in the Two clock cycles are needed for memory read operation – the first one for loading address in the and the next one for loading data from the memory bus into the
The instruction has the register transfer interpretation The minimum number of clock cycles needed for execution cycle of this instruction is:
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Answer: B
To execute the instruction add R0, R1 (which performs ) in a single-bus architecture, we must handle the limitation that only one value can be placed on the shared bus at any given time. The ALU requires two inputs simultaneously to perform an addition.
The execution cycle proceeds as follows:
- Cycle 1: Transfer the first operand from register to the temporary register via the bus.
- Cycle 2: Place the second operand on the bus, instruct the ALU to perform the addition (), and store the result in the temporary output register .
- Cycle 3: Transfer the result from register back to the destination register via the bus.
Thus, a minimum of 3 clock cycles are required for the execution phase of this instruction.
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