GATE CS 2006 Q41 — Memory Hierarchy: Cache, Main Memory and Secondary Storage

To find the total latency of retrieving the cache block, we can break down the process into step-by-step calculations:

1. Analyze the Memory Configuration

• Cache block size: $64$ bytes
• Number of banks ($k$): $24$
• Bank width ($c$): $2$ bytes

2. Determine the Number of Iterations

In a single parallel access, all $k$ banks can be accessed simultaneously. Since each bank is $c$ bytes wide, the maximum data retrieved in one parallel iteration is:

To retrieve a $64$-byte cache block:

• Iteration 1: Accesses all $24$ banks in parallel to retrieve the first $48$ bytes (addresses $0$ to $47$).
• Iteration 2: Accesses the first $8$ banks in parallel to retrieve the remaining $16$ bytes (addresses $48$ to $63$).

Thus, exactly $2$ iterations are required to retrieve the entire cache block.

3. Calculate Latency per Iteration

Each iteration consists of two sequential phases:

1. Decoding phase: Takes $\frac{k}{2}\text{ ns} = \frac{24}{2} = 12\text{ ns}$.
2. Bank access phase: Takes $80\text{ ns}$.

4. Calculate Total Latency

Since the two iterations must be performed sequentially:

Therefore, the correct option is D.