GATE CS 2005 Q65 — Machine Instructions and Addressing Modes

An instruction cycle is divided into two main phases: the Fetch Cycle and the Execution Cycle. The question specifically asks for the number of memory cycles during the execution cycle.

1. Fetch Cycle (Not counted in the execution cycle)

During the fetch phase, the 3-word instruction is fetched from memory:

• Word 1: Opcode and addressing mode specifications (1 memory read)
• Word 2: Address $A$ (1 memory read)
• Word 3: Address $B$ (1 memory read)

After this phase, the values of $A$ and $B$ are already available in the CPU's internal registers.

2. Execution Cycle

During the execution phase, the CPU performs the actual operations and accesses memory to read/write operands:

1. Source Operand ($@B$ - Indirect Addressing):
   • Memory Access 1: Read memory at address $B$ to get the effective address of the source operand, say $EA_{\text{src}} = M[B]$.
   • Memory Access 2: Read memory at $EA_{\text{src}}$ to fetch the actual source operand value.
2. Destination Operand ($A[R_0]$ - Indexed Addressing):
   • The effective address is calculated internally as $EA_{\text{dest}} = A + R_0$ (no memory access needed for this addition).
   • Memory Access 3: Read memory at $EA_{\text{dest}}$ to fetch the destination operand value (required because we need to perform $\text{Destination} + \text{Source}$).
3. ALU Operation:
   • Add the source and destination values (performed inside the CPU, 0 memory accesses).
4. Write Back:
   • Memory Access 4: Write the result back to the destination memory location $EA_{\text{dest}}$.

Summing these up, the total number of memory cycles during the execution cycle is:

Therefore, the correct option is B.