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GATE EC Digital Circuits questions

Practise Digital Circuits questions for GATE EC. Explore official PYQs and original subject-wise quizzes, check answers and view available solutions. Free, no sign-in.

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Official PYQ2017Digital CircuitsComputer OrganizationMCQ · 2 marks
The following FIVE instructions were executed on an 80858085 microprocessor. MVI A, 3333H MVI B, 7878H ADD B CMA ANI 3232H The Accumulator value immediately after the execution of the fifth instruction is
Official PYQ2017Digital CircuitsSequential CircuitsMCQ · 2 marks
A finite state machine (FSM) is implemented using the D flip-flop A and B, and logic gates, as shown in the figure below. The four possible states of the FSM are QAQB=00,01,10Q_{A}Q_{B}=00,01,10 and 1111. Assume that XINX_{IN} is held at a constant logic level throughout the operation of the FSM. When the FSM is initialized to the state QAQB=00Q_{A}Q_{B}=00 and …
Official PYQ2017Digital CircuitsCombinatorial CircuitsMCQ · 1 mark
For the circuit shown in the figure, P and Q are the inputs and Y is the output. The logic implemented by the circuit is
Official PYQ2017Digital CircuitsCombinatorial CircuitsMCQ · 1 mark
Consider the circuit shown in the figure. The Boolean expression FF implemented by the circuit is
Official PYQ2017Digital CircuitsSemiconductor MemoriesMCQ · 1 mark
In a DRAM,
Official PYQ2017Digital CircuitsSequential CircuitsNAT · 2 marks
The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input 'In' and an output 'Out'. The initial state of the FSM is S0S_0. If the input sequence is 1010110100110110101101001101, starting with the left-most bit, then the number of times 'Out' will be 11 is ____________
Official PYQ2017Digital CircuitsCombinatorial CircuitsNAT · 2 marks
Figure Ⅰ shows a 44-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are 2020 ns, 1515 ns and 1010 ns, respectively. Assume all the inputs to the 44-bit adder are initially reset to 00. Figure I Figure II At t=0t = 0, the …
Official PYQ2017Digital CircuitsCombinatorial CircuitsMCQ · 2 marks
A programmable logic array (PLA) is shown in the figure. The Boolean function FF implemented is
Official PYQ2016Digital CircuitsCombinatorial CircuitsMCQ · 1 mark
A small percentage of impurity is added to an intrinsic semiconductor at 300 K300 \: K. Which one of the following statements is true for the energy band diagram shown in the following figure?
Official PYQ2016Digital CircuitsCombinatorial CircuitsMCQ · 1 mark
Consider the following statements for a metal oxide semiconductor field effect transistor (MOSFET): Which of the above statements are INCORRECT? P and Q P and S Q and R R and S
Official PYQ2016Digital CircuitsCombinatorial CircuitsMCQ · 2 marks
The functionality implemented by the circuit below is
Official PYQ2016Digital CircuitsComputer OrganizationMCQ · 2 marks
In an 80858085 system, a PUSH operation requires more clock cycles than a POP operation. Which one of the following options is the correct reason for this?
Official PYQ2016Digital CircuitsSequential CircuitsNAT · 1 mark
Assume that all the digital gates in the circuit shown in the figure are ideal, the resistor R=10ΩR=10\Omega and the supply voltage is 5 V5\:V. The DD flip-flops D1 ,D2 ,D3 ,D4D_{1} \:, D_{2} \:, D_{3} \:, D_{4} and D5D_{5} are initialized with logic values 0,1,0,10,1,0,1 and 00, respectively. The clocks has a 30%30\% duty cycle. The average power dissipated (in …
Official PYQ2016Digital CircuitsCombinatorial CircuitsMCQ · 1 mark
A 4:14:1 multiplexer is to be used for generating the output carry of a full adder. AA and BB are the bits to be added while CinC_{in} is the input carry and CoutC_{out} is the output carry. AA and BB are to be used as the select bits with AA being the more significant select bit. Which one of the following statements correctly describes the …
Official PYQ2016Digital CircuitsSemiconductor MemoriesMCQ · 2 marks
An 88 Kbyte ROM with an active low Chip Select input (CS‾)\left (\overline{CS}\right ) is to be used in an 80858085 microprocessor based system. The ROM should occupy the address range 1000H1000H to 2FFFH2FFFH. The address lines are designated as A15A_{15} to A0A_{0}, where A15A_{15} is the most significant address bit. Which one of the following logic …
Official PYQ2016Digital CircuitsData ConvertersMCQ · 2 marks
In an NN bit flash ADC, the analog voltage is fed simultaneously to 2N−12^{N}-1 comparators. The output of the comparators is then encoded to a binary format using digital circuits. Assume that the analog voltage source VinV_{in} (whose output is being converted to digital format) has a source resistance of 75 Ω75 \: \Omega as shown in the circuit …
Official PYQ2016Digital CircuitsSequential CircuitsMCQ · 2 marks
The state transition diagram for a finite state machine with states AA, BB and CC, and binary inputs XX, YY and ZZ, is shown in the figure. Which one of the following statements is correct?
Official PYQ2016Digital CircuitsCombinatorial CircuitsMCQ · 1 mark
The I−VI-V characteristics of three types of diodes at the room temperature, made of semiconductors X,YX, Y and ZZ, are shown in the figure. Assume that the diodes are uniformly doped and identical in all respects except their materials. If EgXE_{gX},EgYE_{gY} and EgZE_{gZ} are the band gaps of X,YX, Y and ZZ, respectively, then
Official PYQ2016Digital CircuitsComputer OrganizationMCQ · 1 mark
In an 80858085 microprocessor, the contents of the accumulator and the carry flag are A7A7 (in hex) and 00, respectively. If the instruction RLCRLC is executed, then the contents of the accumulator (in hex) and the carry flag, respectively, will be
Official PYQ2016Digital CircuitsCombinatorial CircuitsMCQ · 1 mark
The logic functionality realized by the circuit shown below is