GATE EC 2017 Set 2 Q44 — Combinatorial Circuits

Figure Ⅰ shows a $4$-bit ripple carry adder realized using full adders and Figure Ⅱ shows the circuit of a full-adder (FA). The propagation delay of the XOR, AND and OR gates in Figure Ⅱ are $20$ ns, $15$ ns and $10$ ns, respectively. Assume all the inputs to the $4$-bit adder are initially reset to $0$.

At $t = 0$, the inputs to the $4$-bit adder are changed to $X_3X_2X_1X_0=1100$, $Y_3Y_2Y_1Y_0=0100$ and $Z_0=1$. The output of the ripple carry adder will be stable at $t$ (in ns) = ___________