GATE CS Sequential Circuits questions

The following arrangement of master-slave flip flops has the initial state of $P, Q$ as $0, 1$ (respectively). After three clock cycles the output state $P, Q$ is (respectively),

Consider the following state table for a sequential machine. The number of states in the minimized machine will be …

A finite state machine with the following state table has a single input $x$ and a single out $z$. …

Find the contents of the flip-flop $Q_2, Q_1$ and $Q_0$ in the circuit of figure, after giving four clock pulses to the clock terminal. Assume $Q_2Q_1Q_0=000$ initially.

State True or False with one line explanation A FSM (Finite State Machine) can be designed to add two integers of any arbitrary length (arbitrary number of digits).

For the initial state of $000$, the function performed by the arrangement of the $\text{J-K}$ flip-flops in figure is:

If the state machine described in figure should have a stable state, the restriction on the inputs is given by

Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is $10\;\text{ns}$. Also, assume that the setup time for the $JK$ inputs of the flip flops is negligible.

Advantage of synchronous sequential circuits over asynchronous ones is:

The below figure shows four $\text{D}$-type flip-flops connected as a shift register using a $\text{XOR}$ gate. The initial state and three subsequent states for three clock pulses are also given. …

The above circuit produces the output sequence: