GATE CS 1994 Q3.3 — Sequential Circuits

Correct Answer: True (1)

Explanation:

A Finite State Machine (FSM) can be designed to add two integers of arbitrary length. This is typically implemented as a serial adder.

When adding two numbers bit-by-bit starting from the least significant bit (LSB):

• We only need to keep track of the current carry value, which can only be either $0$ or $1$.
• Thus, the machine requires only two states (State $S_0$ for carry = $0$, and State $S_1$ for carry = $1$).

Since the number of states remains constant (finite) regardless of how many digits the integers have, an FSM is perfectly capable of performing addition on arbitrary-length integers.