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Official PYQ · 1987

GATE CS 1987 Q13-a — Sequential Circuits

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The below figure shows four D\text{D}-type flip-flops connected as a shift register using a XOR\text{XOR} gate. The initial state and three subsequent states for three clock pulses are also given.

StateQAQBQCQDInitial1111After the first clock0111After the second clock0011After the third clock0001\begin{array}{|l|c|c|c|c|} \hline \text{State} & Q_{A} & Q_{B} & Q_{C} & Q_{D} \\ \hline \text{Initial} & 1 & 1 & 1 & 1 \\ \text{After the first clock} & 0 & 1 & 1 & 1 \\ \text{After the second clock} & 0 & 0 & 1 & 1 \\ \text{After the third clock} & 0 & 0 & 0 & 1 \\ \hline \end{array}The state QAQBQCQDQ_{A} Q_{B} Q_{C} Q_{D} after the fourth clock pulse is

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Answer: D

From the given state transitions, we can observe that the circuit is a right-shift register where the bits shift from left to right on each clock pulse:

QB+=QA,QC+=QB,QD+=QCQ_B^+ = Q_A, \quad Q_C^+ = Q_B, \quad Q_D^+ = Q_C

The input to the first flip-flop QAQ_A is fed by the output of the XOR\text{XOR} gate. Let us determine the inputs to this XOR\text{XOR} gate by analyzing the transitions of QAQ_A:

  • Initial State (11111111): Next value of QAQ_A is 00.
  • After 1st clock (01110111): Next value of QAQ_A is 00.
  • After 2nd clock (00110011): Next value of QAQ_A is 00.

An XOR\text{XOR} gate connected to QCQ_C and QDQ_D perfectly satisfies these conditions:

  • At Initial (11111111): QC⊕QD=1⊕1=0Q_C \oplus Q_D = 1 \oplus 1 = 0
  • After 1st clock (01110111): QC⊕QD=1⊕1=0Q_C \oplus Q_D = 1 \oplus 1 = 0
  • After 2nd clock (00110011): QC⊕QD=1⊕1=0Q_C \oplus Q_D = 1 \oplus 1 = 0

Now, we can find the state after the 4th clock pulse using the state after the 3rd clock (00010001):

  • QA+=QC⊕QD=0⊕1=1Q_A^+ = Q_C \oplus Q_D = 0 \oplus 1 = 1
  • QB+=QA=0Q_B^+ = Q_A = 0
  • QC+=QB=0Q_C^+ = Q_B = 0
  • QD+=QC=0Q_D^+ = Q_C = 0

Thus, the state QAQBQCQDQ_A Q_B Q_C Q_D after the fourth clock pulse is 10001000.

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