GATE CS 1987 Q1-III — Sequential Circuits

Consider a $2$-bit saturating up/down counter that performs the saturating up count when the input $P$ is $0$, and the saturating down count when $P$ is $1$. The Next State table of the counter is as shown. The counter is built as a synchronous sequential circuit using D flip-flops. InputCureent StateNext State …

Consider the given sequential circuit designed using D-Flip-flops. The circuit is initialized with some value (initial state). The number of distinct states the circuit will go through before returning back to the initial state is ___________. (Answer in integer)

In a $4$-bit ripple counter, if the period of the waveform at the last flip-flop is $64$ microseconds, then the frequency of the ripple counter in kHz is _________. (Answer in integer)

Consider a sequential digital circuit consisting of $\mathrm{T}$ flip-flops and $\mathrm{D}$ flip-flops as shown in the figure. $\text{CLKIN}$ is the clock input to the circuit. At the beginning, $\text{Q1, Q2}$ and $\text{Q3}$ have values $0,1$ and $1,$ respectively. Which one of the given values of $\text{(Q1, Q2, Q3)}$ can $\text{NEVER}$ …

Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below: Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next three states?

Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered $\text{D}$ flip-flops. The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of "in" is ____