GATE CS 1991 Q03-ii — Sequential Circuits

The correct option is B: ease of avoiding problems due to hazards.

Explanation:

• Asynchronous Sequential Circuits: These circuits do not use a global clock. State transitions occur as soon as the inputs change. Because of unequal propagation delays along different paths, asynchronous circuits are highly susceptible to hazards (temporary glitches) and races (where multiple state variables try to change simultaneously). Designing them to be hazard-free requires complex design techniques, such as adding redundant logic gates or delay elements.
• Synchronous Sequential Circuits: These circuits are governed by a common clock signal. State transitions only occur at the active edge of the clock. By ensuring that the clock period is longer than the maximum propagation delay of the combinational logic, any transient glitches or hazards have sufficient time to settle before the next clock edge. This makes synchronous circuits much easier to design and free from hazard-related issues.

Analysis of other options:

• Option A (Faster operation): Incorrect. Asynchronous circuits are generally faster because they do not have to wait for a clock pulse to transition.
• Option C (Lower hardware requirement): Incorrect. Synchronous circuits typically require more hardware due to the addition of flip-flops and clock distribution networks.
• Option D (Better noise immunity): Incorrect. Noise immunity is primarily a characteristic of the physical logic family (such as CMOS vs. TTL) rather than the synchronicity of the sequential design.