GATE CS Machine Instructions and Addressing Modes questions

Match each addressing mode in $\textbf{List I}$ with a data element or an element of a data structure (in a high-level language) in $\textbf{List II}$: …

Consider a processor $\text{P}$ whose instruction set architecture is the load-store architecture. The instruction format is such that the first operand of any instruction is the destination operand. Which one of the following sequences of instructions corresponds to the high-level language statement $\mathrm{Z}=\mathrm{X}+\mathrm{Y}$ ? Note: X, Y, and Z …

Consider a processor that has $16$ general purpose registers and it uses $2$-byte instruction format for all its instructions. Variable-sized opcodes are permitted. There are three different types of instructions; M-type, R-type, and C-type. Each M-type instruction has $2$ register operands and a $6$-bit immediate operand. Each Rtype instruction has …

A processor has $64$ general-purpose registers and $50$ distinct instruction types. An instruction is encoded in $32$-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction? $\text{ADD R1}$, $\#25$ / / $\text{R 1=R 1+25}$

An application executes $6.4 \times 10^{8}$ number of instructions in $6.3$ seconds. There are four types of instructions, the details of which are given in the table. The duration of a clock cycle in nanoseconds is __________. (rounded off to one decimal place) …

​​​​Which of the following is/are part of an Instruction Set Architecture of a processor?

A processor with $16$ general purpose registers uses a $32$-bit instruction format. The instruction format consists of an opcode field, an addressing mode field, two register operand fields, and a $16$-bit scalar field. If $8$ addressing modes are to be supported, the maximum number of unique opcodes possible for every addressing mode is ___________.

A processor uses a $32$-bit instruction format and supports byte-addressable memory access. The $\text{ISA}$ of the processor has $150$ distinct instructions. The instructions are equally divided into two types, namely $\text{R}$-type and $\text{I}$-type, whose formats are shown below. R - type Instruction Format: \begin{array}{|l|l|l|l|l|} \hline …

Consider the given $\text{C}$-code and its corresponding assembly code, with a few operands $\text{U1-U4}$ being unknown. Some useful information as well as the semantics of each unique assembly instruction is annotated as inline comments in the code. The memory is byte-addressable. //C-code int a[10], b[10], i; // int is 32 bit for(i=0; i<10; i++) …

Consider the following instruction sequence where registers $\text{R1}, \text{R2}$ and $\text{R3}$ are general purpose and $\text{MEMORY[X]}$ denotes the content at the memory location $\text{X}.$ …

A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a $4$-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are $8$ distinct I-type opcodes, then the maximum number of …

A processor has $16$ integer registers $\text{(R0, R1}, \ldots ,\text{ R15)}$ and $64$ floating point registers $\text{(F0, F1}, \ldots , \text{F63)}.$ It uses a $2\text{- byte}$ instruction format. There are four categories of instructions: $\text{Type-1, Type-2, Type-3},$ and $\text{Type-4. Type-1}$ category consists of four instructions, …

Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor?

Consider a RISC machine where each instruction is exactly $4$ bytes long. Conditional and unconditional branch instructions use PC-relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the …

Consider the $C$ struct defined below: struct data { int marks [100]; char grade; int cnumber; }; struct data student; The base address of student is available in register $R1$. The field student.grade can be accessed efficiently using:

Consider a processor with $64$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has $100$ instructions, the …

A processor has $40$ distinct instruction and $24$ general purpose registers. A $32$-bit instruction word has an opcode, two registers operands and an immediate operand. The number of bits available for the immediate operand field is_______.

Consider a processor with byte-addressable memory. Assume that all registers, including program counter (PC) and Program Status Word (PSW), are size of two bytes. A stack in the main memory is implemented from memory location $(0100)_{16}$ and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is …

A machine has a $32\text{-bit}$ architecture, with $1\text{-word}$ long instructions. It has $64$ registers, each of which is $32$ bits long. It needs to support $45$ instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate …

Consider a hypothetical processor with an instruction of type $\text{LW R1, 20(R2)}$, which during execution reads a $32\text{-bit}$ word from memory and stores it in a $32\text{-bit}$ register $\text{R1}$. The effective address of the memory location is obtained by the addition of a constant $20$ and the contents of register $\text{R2}$. Which …