GATE CS Machine Instructions and Addressing Modes questions
Practise Machine Instructions and Addressing Modes questions for GATE CS. Explore official PYQs and original topic-wise quizzes, check answers and view available solutions. Free, no sign-in.
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The use of multiple register windows with overlap causes a reduction in the number of memory accesses for: Function locals and parameters Register saves and restores Instruction fetches
Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor? It must be a trap instruction It must be a privileged instruction An exception cannot be allowed to occur during execution of an RFE instruction
Which of the following is/are true of the auto-increment addressing mode? It is useful in creating self-relocating code If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation The amount of increment depends on the size of the data item accessed
In a simplified computer the instructions are: …
Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction “bbs reg, pos, label” jumps to label if bit in position pos of register operand reg is one. A register is -bits wide and the bits are numbered to bit in position being the least significant. Consider the following emulation of this instruction on a …
A CPU has - instructions. A program starts at address (in decimal). Which one of the following is a legal program counter (all values in decimal)?
Consider the following data path of a The the bus and all the registers in the data path are of identical size. All operations including incrementation of the and the are to be carried out in the Two clock cycles are needed for memory read operation – the first one for loading …
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side. …
Consider a three word machine instruction The first operand (destination) uses indexed addressing mode with as the index register. The second operand (source) uses indirect addressing mode. and are memory addresses residing at the second and third words, respectively. The first word of the …
Consider the following program segment for a hypothetical CPU having three user registers and \begin{array}{|l|l|c|} \hline \text {Instruction} & \text{Operation }& \text{Instruction size (in Words)} \\\hline \text{MOV } & \text{} \leftarrow \text{Memory}& \text{} \\\hline\text{MOV …
Consider the following program segment for a hypothetical CPU having three user registers and …
Which of the following addressing modes are suitable for program relocation at run time? Absolute addressing Based addressing Relative addressing Indirect addressing
Consider the following assembly language program for a hypothetical processor and are bit registers. The meanings of various instructions are shown as comments. MOV B, #0 ; MOV C, #8 ; Z: CMP C, #0 ; compare C with 0 JZ X ; jump to X if zero flag is set SUB C, #1 ; RRC A, #1 ; right …
Consider the following assembly language program for a hypothetical processor and are bit registers. The meanings of various instructions are shown as comments. …
In the absolute addressing mode:
Which of the following is not a form of memory
Which is the most appropriate match for the items in the first column with the items in the second column: …
Suppose a processor does not have any stack pointer registers, which of the following statements is true?
A low memory can be connected to 8085 by using
The most appropriate matching for the following pairs is