GATE CS Combinational Circuits questions

Practise Combinational Circuits questions for GATE CS. Explore official PYQs and original topic-wise quizzes, check answers and view available solutions. Free, no sign-in.

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SubjectTopicYearType

Consider the circuit shown below. In a certain steady state, the line

Y

is at

'1'

. What are the possible values of

A, B

and

C

in this state?

The threshold level for logic 1 in the TTL family is

A multiplexer with a

4-bit

data select input is a

Consider a logic circuit shown in figure below. The functions

f_1, f_2 \text{ and } f

(in canonical sum of products form in decimal notation) are :

f_1 (w, x, y, z) = \sum 8, 9, 10

f_2 (w, x, y, z) = \sum 7, 8, 12, 13, 14, 15

f (w, x, y, z) = \sum 8, 9

The function

f_3

Consider the circuit in figure.

f

implements

Consider the circuit in below figure which has a four bit binary number

b_3b_2b_1b_0

as input and a five bit binary number,

d_4d_3d_2d_1d_0

as output.

A ROM is used to store the table for multiplication of two

8

-bit unsigned integers. The size of ROM required is

The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How many separate address and data lines are needed for a memory of

4K \times 16

The logic expression for the output of the circuit shown in figure below is:

Identify the logic function performed by the circuit shown in figure.

All digital circuits can be realized using only

State whether the following statements are TRUE or FALSE with reason: RAM is a combinational circuit and PLA is a sequential circuit.

Choose the correct alternatives (More than one may be correct). Two NAND gates having open collector outputs are tied together as shown in below figure. The logic function

Y,

implemented by the circuit is,

The output

F

of the below multiplexer circuit can be represented by