GATE CS Digital Logic questions

In the Karnaugh map shown below, $X$ denotes a don’t care term. What is the minimal form of the function represented by the Karnaugh map?

In the IEEE floating point representation the hexadecimal value $0\text{x}00000000$ corresponds to

Which of the following is TRUE about formulae in Conjunctive Normal Form?

The control signal functions of a $4$-$bit$ binary counter are given below (where $X$ is “don’t care”): …

In a look-ahead carry generator, the carry generate function $G_i$ and the carry propagate function $P_i$ for inputs $A_i$ and $B_i$ are given by: $$P_i = A_i \oplus B_i \text{ and }G_i = A_iB_i$$ The expressions for the sum bit $S_i$ and the carry bit $C_{i+1}$ of the look ahead carry adder are given by: …

Suppose only one multiplexer and one inverter are allowed to be used to implement any Boolean function of $n$ variables. What is the minimum size of the multiplexer needed?

Define the connective $*$ for the Boolean variables $X$ and $Y$ as: $$X * Y = XY + X'Y'.$$ Let $Z = X * Y$. Consider the following expressions $P$, $Q$ and $R$. $$P : X = Y * Z, \\ Q :Y = X * Z, \\ R : X *Y * Z = 1$$ Which of the following is TRUE?

Let $f(w, x, y, z) = \sum {\left(0,4,5,7,8,9,13,15\right)}$. Which of the following expressions are NOT equivalent to $f$? P: $x'y'z' + w'xy' + wy'z + xz$ Q: $w'y'z' + wx'y' + xz$ R: $w'y'z' + wx'y' + xyz+xy'z$ S: $x'y'z' + wx'y'+ w'y$

Consider the following Boolean function of four variables: $$f(w, x, y, z) = \Sigma(1, 3, 4, 6, 9, 11, 12, 14)$$ The function is

How many $3$-to-$8$ line decoders with an enable input are needed to construct a $6$-to-$64$ line decoder without using any other logic gates?

Consider numbers represented in 4-bit Gray code. Let $h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $g_{3}g_{2}g_{1}g_{0}$ be the Gray code of $(n+1)(modulo 16)$ value of the number. Which one of the following functions is correct?

We consider the addition of two $2's$ complement numbers $b_{n-1}b_{n-2}\dots b_{0}$ and $a_{n-1}a_{n-2}\dots a_{0}$. A binary adder for adding unsigned binary numbers is used to add the two numbers. The sum is denoted by $c_{n-1}c_{n-2}\dots c_{0}$ and the carry-out by $c_{out}$. Which one of the following options correctly identifies the overflow …

Consider a Boolean function $f(w,x,y,z)$. Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors $i_{1}=\left \langle w_{1}, x_{1}, y_{1},z_{1}\right \rangle$ and $i_{2}=\left \langle w_{2}, x_{2}, y_{2},z_{2}\right \rangle$ , we would like the function to remain true as the input …

Consider the circuit in the diagram. The $\oplus$ operator represents Ex-OR. The D flip-flops are initialized to zeroes (cleared). The following data: $100110000$ is supplied to the “data” terminal in nine clock cycles. After that the values of $q_{2}q_{1}q_{0}$ are:

Given two three bit numbers $a_{2}a_{1}a_{0}$ and $b_{2}b_{1}b_{0}$ and $c$ the carry in, the function that represents the carry generate function when these two numbers are added is:

Consider the circuit above. Which one of the following options correctly represents $f\left(x,y,z\right)$

You are given a free running clock with a duty cycle of $50\%$ and a digital waveform $f$ which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of $f$ by $180°$?

Consider the following floating-point format. Mantissa is a pure fraction in sign-magnitude form. The normalized representation for the above format is specified as follows. The mantissa has an implicit $1$ preceding the binary (radix) point. Assume that only $0’s$ are padded in while shifting a field. The normalized representation of the above number …

Consider the following floating-point format. Mantissa is a pure fraction in sign-magnitude form. The decimal number $0.239 \times 2^{13}$ has the following hexadecimal representation (without normalization and rounding off):

Consider the following circuit: The flip-flops are positive edge triggered $D$ $\textsf{FF}$s. Each state is designated as a two-bit string $Q_0Q_1$. Let the initial state be $00.$ The state transition sequence is