You are given a free running clock with a duty cycle of and a digital waveform which changes only at the negative edge of the clock. Which one of the following circuits (using clocked D flip-flops) will delay the phase of by ?
View worked solution
Answer: C
A phase delay of corresponds to exactly half of a clock period () because the clock has a duty cycle.
The input waveform changes only at the negative edge of the clock. To delay by , we need the output to change at the positive edge of the clock, which occurs exactly half a cycle after the negative edge.
This behavior is achieved by passing through a positive-edge triggered D flip-flop. A positive-edge triggered D flip-flop is represented without a bubble on its clock input, as shown in Option C.
Free practice · Your answers on this page are not saved.