GATE CS Combinational Circuits questions

Consider the digital circuit shown below with two input lines $\text{A}$ and $\text{B}$, two select lines $\text{S0}$ and $\text{S1}$, and an output line $\text{Y}$. The blocks $\text{Q}$ and $\text{M}$ represent active high $2:4$ decoder and $4$-to-$1$ multiplexer, respectively. Out of $16$ possible input combinations, the number of …

​Consider the following logic circuit diagram. Which is/are the CORRECT option(s) for the output function $F$ ?

​​Consider the circuit shown below where the gates may have propagation delays. Assume that all signal transitions occur instantaneously and that wires have no delays. Which of the following statements about the circuit is/are CORRECT?

Consider a digital logic circuit consisting of three $2$-to-$1$ multiplexers $\text{M1, M2}$, and $\text{M3}$ as shown below. $\mathrm{X} 1$ and $\mathrm{X} 2$ are inputs of $\mathrm{M} 1$. $\text{X3}$ and $\text{X4}$ are inputs of $\text{M2}$. $\text{A, B}$, and $\text{C}$ are select lines of $\text{M1, M2}$, and $\text{M3}$, …

The output of a $2$-input multiplexer is connected back to one of its inputs as shown in the figure. Match the functional equivalence of this circuit to one of the following options.

A Boolean digital circuit is composed using two $4$-input multiplexers $\text{(M1 and M2)}$ and one $2$-input multiplexer $\text{(M3)}$ as shown in the figure. $\text{X0-X7}$ are the inputs of the multiplexers $\text{M1 and M2}$ and could be connected to either $0$ or $1.$ The select lines of the multiplexers are connected to Boolean …

Consider a digital display system $\text{(DDS)}$ shown in the figure that displays the contents of register $\text{X}.$ A $16 – \text{bit}$ code word is used to load a word in $\text{X},$ either from $\text{S}$ or from $\text{R}.$ $\text{S}$ is a $1024-$word memory segment and $\text{R}$ is a $32-$word register file. Based on the value of …

Which one of the following circuits implements the Boolean function given below? $f(x,y,z) = m_0+m_1+m_3+m_4+m_5+m_6$, where $m_i$ is the $i^{\text{th}}$ minterm.

A multiplexer is placed between a group of $32$ registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The number of select lines needed for the multiplexer is ______.

If there are $m$ input lines and $n$ output lines for a decoder that is used to uniquely address a byte addressable $1$ KB RAM, then the minimum value of $m+n$ is ________ .

Consider the two cascade $2$ to $1$ multiplexers as shown in the figure . The minimal sum of products form of the output $X$ is

Consider the $4\text{-to-1}$ multiplexer with two select lines $S_1$ and $S_0$ given below The minimal sum-of-products form of the Boolean expression for the output $F$ of the multiplexer is

The above synchronous sequential circuit built using JK flip-flops is initialized with $Q_2Q_1Q_0 = 000$. The state sequence for this circuit for the next $3$ clock cycles is

Consider the following combinational function block involving four Boolean variables $x,\:y,\:a,\:b$ where $x,\:a,\:b$ are inputs and $y$ is the output. f(x, a, b, y) { if(x is 1) y = a; else y = b; } Which one of the following digital logic blocks is the most suitable for implementing this function?

In the following truth table, $V = 1$ if and only if the input is valid. …

The amount of ROM needed to implement a $4\text{-bit}$ multiplier is

Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. If all the flip-flops were reset to $0$ at power on, what is the total number of distinct outputs (states) represented by $PQR$ generated by the counter?

In the sequential circuit shown below, if the initial value of the output $Q_1Q_0$ is $00$. What are the next four values of $Q_1Q_0$?

What is the boolean expression for the output $f$ of the combinational logic circuit of NOR gates given below?

The Boolean expression of the output $f$ of the multiplexer shown below is