GATE CS 2007 Q36 — Combinational Circuits

Based on the standard circuit diagram for this question:

• An AND gate is connected to the Clear input of the counter.
• The inputs to this AND gate are $Q_2$ and $Q_0$. Therefore, $\text{Clear} = Q_2 \cdot Q_0$.
• The Count input is active ($1$) and Load is inactive ($0$).

Let's trace the counter states starting from $0$ ($0000_2$):

1. For states $0, 1, 2, 3,$ and $4$, the condition $Q_2 = 1$ and $Q_0 = 1$ is not met. Thus, $\text{Clear} = 0$, and the counter increments normally on each clock edge: $$0 \to 1 \to 2 \to 3 \to 4$$
2. On the next clock edge, the counter increments from $4$ ($0100_2$) to $5$ ($0101_2$).
3. At state $5$, we have $Q_2 = 1$ and $Q_0 = 1$, which makes the AND gate output $\text{Clear} = 1$.
4. According to the function table, when $\text{Clear} = 1$, the counter is cleared to $0$ asynchronously (independent of the clock).

Since gate and counter delays are negligible, state $5$ is highly transient and immediately resets to $0$. Thus, the stable sequence of states is $0, 1, 2, 3, 4$.