GATE CS 2006 Q39 — Number Representations (Fixed and Floating Point)

In $2$'s complement representation, the most significant bit (MSB) acts as the sign bit ($0$ for positive numbers and $1$ for negative numbers). Here, the sign bits of the two numbers are $a_{n-1}$ and $b_{n-1}$, and the sign bit of the resulting sum is $c_{n-1}$.

An overflow in $2$'s complement addition occurs if and only if adding two numbers of the same sign yields a result with the opposite sign. Adding two numbers of opposite signs can never result in an overflow.

This gives us two mutually exclusive scenarios for overflow:

1. Adding two negative numbers yields a positive sum:
   • Both inputs are negative: $a_{n-1} = 1$ and $b_{n-1} = 1$
   • The sum is positive: $c_{n-1} = 0$
   • Boolean term: $a_{n-1} b_{n-1} \overline{c_{n-1}}$
2. Adding two positive numbers yields a negative sum:
   • Both inputs are positive: $a_{n-1} = 0$ and $b_{n-1} = 0$
   • The sum is negative: $c_{n-1} = 1$
   • Boolean term: $\overline{a_{n-1}} \, \overline{b_{n-1}} c_{n-1}$

Combining these two conditions using the logical OR operator, we get the complete overflow condition:

This matches Option B.