GATE CS 2007 Q8 — Combinational Circuits

To construct a $6$-to-$64$ line decoder using $3$-to-$8$ line decoders with enable inputs, we can design the circuit in a hierarchical (tree) structure:

1. Output Stage (First Level): To produce $64$ output lines, we need $3$-to-$8$ decoders at the output stage. Since each decoder provides $8$ outputs: $$\text{Number of decoders in the first level} = \frac{64}{8} = 8$$ These $8$ decoders will share the same $3$ lower-order input lines ($I_2, I_1, I_0$).
2. Control Stage (Second Level): To ensure only one of the $8$ output decoders is active at any given time, we need to decode the remaining $3$ higher-order input lines ($I_5, I_4, I_3$). We can use another $3$-to-$8$ decoder to decode these $3$ inputs. Its $8$ outputs will connect directly to the enable ($E$) inputs of the $8$ decoders in the output stage. $$\text{Number of decoders in the second level} = 1$$

Thus, the total number of $3$-to-$8$ decoders required is:

Since the control decoder's outputs directly drive the enable inputs of the output decoders, no additional logic gates are required.