GATE CS 2002 Q2.6 — Instruction Pipelining

The performance of a pipelined processor is optimized when instructions flow smoothly through all stages without interruption. Performance suffers due to the following reasons corresponding to each option:

• A. Different stage delays: The clock cycle time of a pipeline is determined by the slowest stage ($T_{\text{clock}} = \max(t_1, t_2, \dots, t_k) + d$). If stages have highly unequal delays, faster stages remain idle waiting for the slowest stage, leading to inefficiency.
• B. Dependency between consecutive instructions: This introduces data hazards. When an instruction depends on the result of a previous instruction that has not yet written back its result, the pipeline must stall (insert bubbles) or use complex forwarding paths, reducing throughput.
• C. Shared hardware resources: This causes structural hazards. If two different stages require the same physical resource (e.g., a single memory port for both Instruction Fetch and Data Access) at the same time, one of the instructions must be stalled.

Since all three scenarios (A, B, and C) degrade pipeline performance, the correct option is D.