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Official PYQ · 1987Q2aI/O Interface: Interrupt and DMA ModeNAT1 mark

GATE CS 1987 Q2a — I/O Interface: Interrupt and DMA Mode

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State whether the following statements are TRUE or FALSE

In a microprocessor-based system, if a bus (DMA) request and an interrupt request arrive sumultaneously, the microprocessor attends first to the bus request.
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Answer: 1

The given statement is TRUE (represented by 1).

Explanation:

In a microprocessor-based system, a DMA (Direct Memory Access) request (also known as a bus request) has a higher priority than an Interrupt request due to the following reasons:

  1. Sampling Frequency:
    • The microprocessor samples DMA requests (such as HOLD) at the end of every machine cycle.
    • In contrast, interrupt requests (such as INTR) are sampled only at the end of the current instruction cycle (which consists of multiple machine cycles).
  2. Time Sensitivity: DMA is used for high-speed data transfer where any delay can lead to data loss from fast I/O devices. Interrupts are less time-critical and can safely wait until the current instruction completes.

Therefore, if both requests arrive simultaneously, the microprocessor services the bus (DMA) request first.

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