GATE CS 2000 Q1.8 — Instruction Pipelining

To compare the time taken for a single instruction on a pipelined CPU ($T_1$) versus a non-pipelined CPU ($T_2$), let us analyze how instruction execution time is determined in both cases.

1. Non-Pipelined CPU ($T_2$)

In a non-pipelined CPU, an instruction is executed sequentially through all its stages. The total time taken ($T_2$) is the sum of the delays of each individual stage:

where $t_i$ is the delay of stage $i$, and $k$ is the number of stages.

2. Pipelined CPU ($T_1$)

In a pipelined CPU, the clock cycle time ($t_p$) is determined by the slowest stage delay plus the overhead of the pipeline registers ($\tau_{reg}$):

Since a single instruction must pass through all $k$ stages to complete, the total time taken for one instruction to go from start to finish (latency) is:

Comparison

Because the clock period of the pipeline is bounded by the slowest stage, any stage that is faster than the slowest stage must still wait for the full duration $t_p$. Additionally, the pipeline registers introduce setup and propagation delays ($\tau_{reg} \ge 0$).

Mathematically, since $\max(t_i) \ge t_i$ for all $i$:

Therefore, we have:

Thus, a single instruction takes more time (or at least equal time) to complete in a pipelined CPU compared to an identical non-pipelined CPU. Pipelining improves throughput (the rate of instruction completion), not the latency of an individual instruction.