GATE CS Computer Organization and Architecture questions

Practise Computer Organization and Architecture questions for GATE CS. Explore official PYQs and original subject-wise quizzes, check answers and view available solutions. Free, no sign-in.

Track address sizes, cache organisation and pipeline dependencies carefully. Write down the units and assumptions before computing memory access times or processor performance.

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SubjectTopicYearType

Consider the following assembly language program for a hypothetical processor

A, B,

and

C

are

8-

bit registers. The meanings of various instructions are shown as comments. …

For a pipelined CPU with a single ALU, consider the following situations The

{j+1}^{st}

instruction uses the result of the

j^{th}

instruction as an operand The execution of a conditional jump instruction The

j^{th}

and

{j+1}^{st}

instructions require the ALU at the same time. Which of the above can cause a hazard

Horizontal microprogramming:

The performance of a pipelined processor suffers if:

In the absolute addressing mode:

Which of the following is not a form of memory

A device employing INTR line for device interrupt puts the CALL instruction on the data bus while:

Consider the following data path of a simple non-pipelined CPU. The registers

A, B

A_{1},A_{2}, \textsf{MDR},

the

\textsf{bus}

and the

\textsf{ALU}

are

8

bit

wide.

\textsf{SP}

and

\textsf{MAR}

are

16

bit

registers. The

\textsf{MUX}

is of size

8 \times (2:1)

and the

\textsf{DEMUX}

is of size …

Which is the most appropriate match for the items in the first column with the items in the second column: …

Suppose a processor does not have any stack pointer registers, which of the following statements is true?

A low memory can be connected to 8085 by using

More than one word are put in one cache block to:

The most appropriate matching for the following pairs

\begin{array}{ll} \text{X: Indirect addressing} & \text{1: Loops } \\ \text{Y: Immediate addressing } & \text{2: Pointers} \\ \text{Z: Auto decrement addressing } & \text{3: Constants } \\ \end{array}

Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but identical CPU, we can say that

To put the 8085 microprocessor in the wait state

An instruction pipeline consists of

4

stages – Fetch

(F)

, Decode field

(D)

, Execute

(E)

and Result Write

(W)

. The

5

instructions in a certain instruction sequence need these stages for the different number of clock cycles as shown by the table below …

The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically

A certain processor supports only the immediate and the direct addressing modes. Which of the following programming language features cannot be implemented on this processor?

Arrange the following configuration for CPU in decreasing order of operating speeds: Hard wired control, Vertical microprogramming, Horizontal microprogramming.

The main memory of a computer has

2\;\text{cm}

blocks while the cache has

2\;\text{c}

blocks. If the cache uses the set associative mapping scheme with

2

blocks per set, then block

k

of the main memory maps to the set: