GATE CS 2001 Q2.13 — ALU, Data-path and Control Unit

To execute the push r instruction, we need to perform the memory write operation $M[SP] \leftarrow r$ and decrement the stack pointer $SP \leftarrow SP - 1$. The clock cycle distribution is as follows:

1. Transferring $SP$ to $MAR$ (2 cycles): Since $SP$ and $MAR$ are 16-bit registers but the CPU data bus is only 8-bit wide, the transfer must occur in two 8-bit steps:
   • Cycle 1: $MAR_H \leftarrow SP_H$
   • Cycle 2: $MAR_L \leftarrow SP_L$
2. Transferring data to $MDR$ (1 cycle):
   • Cycle 3: $MDR \leftarrow r$ (since $r$ and $MDR$ are 8-bit wide, this takes 1 cycle via the 8-bit bus).
3. Memory Write & SP Decrement (2 cycles):
   • Cycles 4 and 5: The memory write operation $M[MAR] \leftarrow MDR$ takes 2 CPU clock cycles.
   • In parallel, the local decrement $SP \leftarrow SP - 1$ is performed locally, requiring 0 additional cycles.

Therefore, the total number of CPU clock cycles required is $2 + 1 + 2 = 5$ cycles.